1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for providing a context switch when an interrupt in a computer process occurs.
2. History of the Prior Art
Historically, when a computer process is running and it is necessary to interrupt that process and run another process which should be run before the running process completes, the computer processor stops running the process, stores in some convenient memory the various information about the process being run which establishes the context of that process and which is necessary to restart that process, then utilizes the registers of the processor to run the interrupting process until it is complete, and finally recalls the information relating to the interrupted process to the registers, and recommences running the interrupted process.
In general, this is a relatively straight forward but slow operation since memory must be accessed a number of times to store and recall the information relating to the state of the process which is interrupted. However, there are situations in which such a straight-line interrupt operation cannot be used. For example, a new form of memory referred to as flash electrically-erasable programmable read only memory (flash EEPROM) has recently been developed as a substitute for conventional long term storage such as hard disk drives. This flash EEPROM memory utilizes an array of floating gate field effect transistors which are placed into erased and programmed states by varying the charge on the floating gate. Typically, the devices are placed in the erased condition by providing a high positive voltage such as twelve volts on the source terminals of all of the devices in a selected block of the array while grounding the gate terminals and floating the drain terminals of the devices in the block. For various reasons, the erase process is quite time consuming and may take as long as two seconds. Typically, each device is individually programmed by applying a high voltage such as twelve volts to the gate terminal while applying a lower voltage to the drain terminal and grounding the source terminal. In contrast to erasing, programming is a very rapid process. The devices are read by applying much lower voltages to the gate terminals of the devices and determining the tendency of each device to transfer current.
Because flash EEPROM arrays are erased and programmed by levels of voltage which are much higher than are the normal voltages used to interrogate the array, these erasing and programming voltages must be applied in very precise sequences at very precise times in order to operate the array without loss of data or harm to the array. However, because the erase process is such a time consuming process, it is often desirable to interrupt that process in order to accomplish other operations. When the erase process is interrupted, it is necessary that the a number of tasks be completed in addition to the normal tasks typical to an interrupt. For example, it is necessary that the various sources of high voltage be shut down in an orderly fashion so that the data and the devices of the array not be harmed. When the interrupting process has completed, it is necessary that the various steps required for restarting the erase process be completed in an orderly fashion with the high voltages being reapplied at the appropriate point in the sequence of the erase operation so that damage to the devices of the array or the data stored does not occur. This may mean that the interrupted process cannot not be restarted without running one or more intervening processes required for startup of the erase or other interrupted process rather than simply returning to the interrupted process where it was interrupted.
An arrangement has been designed which accomplishes just such a unique interrupt operation. Such an arrangement is described in detail in U.S. patent application Ser. No. 08/086,186, entitled Flash Memory Array System and Method, M. Fandrich et al, filed on even date herewith, and assigned to the assignee of the present invention. The arrangement includes an interrupt start process or routine (ISR) and an interrupt return process (IRR). The ISR process and the IRR process are included in each interruptible process (such as the erase process) and guide the processor through the steps peculiar to the process being interrupted to provide an orderly shutdown and restart so that the array is not adversely affected. It will be appreciated that the necessity to provide these ISR and IRR processes in the software of each interruptible process lengthens the interrupt operation substantially. For this reason it is very desirable to provide circuitry and a method by which any interruptible process may be accelerated when a processor utilizes this type of interrupt.